What changed and when

• Completed extended state-lifecycle and checkpoint validation across the 40-byte zero-allocation SDK context and expanded the automated verification suite to 79 formal and functional test cases across all 16 cipher and companion primitives.
• Refined public release documentation and technical summaries to focus strictly on external API capabilities, formal verification outcomes, and hardware SWaP-C benchmark results.

• Standardized fail-closed API input and entropy validation across stream, seekable storage, and random bit generator interfaces, and introduced selectable compile-time build profiles (default hybrid, compact flash, and full-speed) that preserve 100% bit-exact Known Answer Test compatibility while reducing embedded instruction-cache footprint.
• Completed on-silicon benchmarking on constrained ESP32-S3 and RISC-V hardware (cycle-accurate timing, synchronized power profiling, stack usage, and code-size tracking) to characterize size- and energy-optimized build profiles.

• Added high-throughput word-rate companion modes and accelerated stream processing options, delivering 3.4x to 8.0x throughput gains across bulk stream encryption, hashing, MAC, KDF, seekable sector storage, and AEAD within the fixed 40-byte zero-allocation context.
• Expanded the standalone Known Answer Test verification harness to cover all 16 core and companion primitive modes with 100% cross-platform parity.

• Added hardware side-channel masking, extended 256-bit nonce support (2128 random-nonce collision bound), and automatic forward-secrecy stream ratcheting within the fixed 40-byte zero-allocation context.

• Completed the 38-tool formal verification, symbolic analysis, side-channel evaluation, and hardware RTL synthesis battery with a certified 4.0x to 24.0x security margin across the 24-round initialization schedule.
• Verified the synthesizable Verilog-2005 hardware core and AXI4-Stream wrapper under formal synthesis and SMT equivalence checking alongside NIST SP 800-90B min-entropy validation.

• Certified zero static RAM overhead (0 B heap, 0 B static .bss/.data) and constant-time machine-code execution across x86_64, 32-bit Xtensa LX7 (ESP32-S3), ARM Cortex-M, and 32-bit RISC-V targets.
• Expanded host and embedded integration wrappers (C/C++, Python bindings, mbedTLS cipher interface, and OTA Secure Boot loader) and verified multi-gigabyte PractRand statistical streams across all companion modes with zero anomalies.

• Standardized the unified 40-byte zero-allocation context and companion primitive APIs (HASH, MAC, KDF, AEAD, DRBG, VFS, CFB, FPE, and STEALTH) with formal Coq and Z3 SMT verification of state bijectivity and mode isolation.
• Completed constant-time binary analysis across 24 GCC and Clang build configurations and validated deep-sleep state checkpoint serialization for duty-cycled embedded sensors.

• Executed physical hardware-in-the-loop benchmarks on ESP32-S3 and 915 MHz LoRa testbeds with live Nordic PPK2 power profiling and 10,000-node discrete-event network simulations.
• Published formal SMT verification summaries, statistical test results (NIST SP 800-22, TestU01 BigCrush, and 32 TB PractRand), and multi-compiler constant-time verification metrics on the Validation & SMT Tests page.

• Launched the expanded public architecture documentation: How It Works, APEX-256 with ASCON, FAQ, Glossary, Field Notes, Security & Review, and Revision History.
• Published downloadable federal contractor capabilities documentation, security review contact details, and PGP key material.

Any test vector published or circulated before the current 24-round initialization is withdrawn. The evaluation kit carries the current set.

• Independent cryptanalysis of the cipher.
• On-silicon evaluation of the APEX-256 and ASCON pairing.
• Published, reproducible cycle, flash and energy measurements.