FAQ

Use them if you can. AES-GCM and ChaCha20-Poly1305 are what you should reach for when you have the RAM, the code space, and a link that can take the extra bytes. APEX-256 is for the devices where you don’t.

ASCON is a good standard for small devices. We don’t compete with it; we pair with it. See APEX-256 with ASCON.

The raw APEX-256 stream cipher only encrypts so that ciphertext stays the same length as plaintext. For authenticated encryption, the SDK includes APEX-AEAD (with standard 64-bit nonces, 256-bit X256 nonces, and word-rate W64 acceleration), or you can pair it with a NIST standard AEAD like ASCON-128. How It Works explains why and how.

No. It is not a NIST standard and it is not FIPS validated. If you need standardized primitives, use the pairing described on the ASCON page.

The key exchange is, when you use a standardized KEM. The cipher itself is a 256-bit symmetric primitive, and we don’t call it a post-quantum algorithm.

Not yet. We would like someone to try. Here is how.

16 cryptanalysis waves and a 38-tool external formal/SMT/SAT/MILP/SCA/RTL battery (Z3, Bitwuzla, cvc5, CaDiCaL, Coq, F*, HiGHS, SCALib, Lascar, VerFI, SymbiYosys), a 7-engine reduced-round safety-margin certification (4.0x to 24.0x margin), 32 TB of PractRand, BigCrush, NIST SP 800-22, and power captures on real boards. The tables and the caveats are on Validation.

So the message does not grow. Output is exactly as long as input and there is nothing to pad or fragment. The cost is discipline: you must never reuse a key and nonce pair, and you need an authentication layer.

Same as any stream cipher: the keystream repeats, and an attacker who XORs two ciphertexts gets the XOR of the two plaintexts. To prevent accidental collisions when generating random nonces at scale, the engine also provides extended 256-bit nonces (X256), expanding random-nonce birthday safety from 232 to 2128 messages with zero added RAM, plus 256-byte forward-secrecy keyframe ratcheting.

Under an evaluation NDA. Patent applications are pending, and the reference implementation, constants and test vectors are restricted. Request access.

ARM Cortex-M4/M7 (STM32F405, STM32H757), ESP32-S3, Nordic nRF52840, RISC-V, and synthesizable Verilog-2005 FPGA cores in our lab. Details on Hardware.

Three tiers: a free academic review under NDA, a commercial pilot evaluation kit, and a full production license. See Licensing.

Protected by pending U.S. and International Patent Applications. Nothing is granted yet.

One person: Diab Anthony Sheteyh, in Henderson, Nevada. The full story is here.